FPGA-based Low-power Speech Recognitionwith Recurrent Neural Networks
TABLE I: The WER and the CER performance (%) of the SR algorithm with respect to the beam width.
['Network', 'Word LM', 'Beam width', 'WER / CER']
The word error rate (WER) and character error rate ( CER) performances of the proposed system with respect to the size of the RNNs and The small-model represents the system with 3×256 RNN AM and 2×256 RNN LM while the large-model employs 4×512 RNN AM and 2×512 RNN LM. The table shows that the performance improves when the beam width or the network size increases. Also, combining the word-level LM improves the performance especially when the network size is small. Of course, the best advantage we expect is the energy efficiency since we do not employ a WFST network which demands a large amount of computation and memory accesses. The algorithm also uses the WFST decoding network to combine the results of acoustic modeling, lexicon, and the word-level LM. Note that the compared system does not use the character-level RNN because the WFST network embeds the lexicon. However, the WFST-based decoding demands a large memory space to search, and thus the algorithm is hard to be power efficient. On the other hand, our algorithm employs the character-level LM in addition to the word-level LM, and uses simple beam-search in decoding that requires far less memory. The RNNs of the proposed algorithm are implemented using only on-chip memory for energy efficiency. Note that the recognition performance of our system can be further improved by employing larger RNNs or increasing the beam width.