         dim4 src_stride, dim4 tgt_stride, dim4 size, Op op, T init)
 {
   const size_t reduce = 3;
-  uint col = blockIdx.x * blockDim.x + threadIdx.x;
+  unsigned col = blockIdx.x * blockDim.x + threadIdx.x;
   float *src = src_ + blockIdx.z * src_stride[2] + blockIdx.y * src_stride[1] + col;
 
   if(col < size[0]) {
     T acc = init;
-    for(uint i=0; i < size[reduce]; i++) {
+    for(unsigned i=0; i < size[reduce]; i++) {
       acc = op((T) acc, (T) *src);
       src += src_stride[reduce];
     }

  dim4 tgt_stride(0);
  dim4 size(1);

  uint ndim = THCudaTensor_nDimension(src);
  for(uint idim=0, o=ndim-2; idim < ndim; idim++) {
    uint odim = idim == rdim ? reduce : o--;
    src_stride[odim] = THCudaTensor_stride(src, idim);
    tgt_stride[odim] = THCudaTensor_stride(tgt, idim);
    size[odim]       = THCudaTensor_size(src, idim);
  }

  const uint nThreadPerBlock = 256;
  uint nBlockPerColumn = (size[0] + nThreadPerBlock - 1) / nThreadPerBlock;
  dim3 threads(nThreadPerBlock);
  dim3 grid(nBlockPerColumn, size[1], size[2]);



  T acc = init;

  unsigned row = blockIdx.y * blockDim.y + threadIdx.y;
  float *src = src_ + blockIdx.z * src_stride[3] + blockIdx.x * src_stride[2] + row * src_stride[1];
  bool reducing = threadIdx.x < blockDim.y
                && blockIdx.y * blockDim.y + threadIdx.x < size[1]
                && threadIdx.y == 0;

  for(unsigned bCol=0; bCol < size[0]; bCol += blockDim.x) {

    sbuf[threadIdx.y][threadIdx.x] = init;
    unsigned col = bCol + threadIdx.x;
    if(row < size[1] && col < size[0]) {
      sbuf[threadIdx.y][threadIdx.x] = src[col];
    }
    __syncthreads();

    if(reducing) {
      for(unsigned x=0; x < blockDim.x; ++x) {
        /* Could eliminate shared memory bank conflicst hare by using modulo 32
         * addressing: (x + threadIdx) % 32. However, due to the memory-bound
         * nature of the kernel this makes no difference to performance */
