     int lane = threadIdx.x % 32; // from 0 to 31
 
     // if less than 1024 threads per block, then only activate the relevant lanes
-    if (lane < blockDim.x / 32) 
+    if (lane < blockDim.x / 32)
     {
 #pragma unroll
       for (int i = 0; i < 32; ++i)

{
  THCUNN_assertSameGPU(state, 2, input, output);

  input = THCudaTensor_newContiguous(state, input);
  THCudaTensor_resizeAs(state, output, input);

  int batchSize = 1;
  int classSize = 0;
  int stride    = 1;

  if (THCudaTensor_nDimension(state, input) == 1)
  {
    classSize = THCudaTensor_size(state, input, 0);
  }
  else if (THCudaTensor_nDimension(state, input) == 2)
  {
    batchSize = THCudaTensor_size(state, input, 0);
    classSize = THCudaTensor_size(state, input, 1);
  }
  else if (THCudaTensor_nDimension(state, input) == 3)
  {
    classSize = THCudaTensor_size(state, input, 0);
    stride = THCudaTensor_size(state, input, 1)*
             THCudaTensor_size(state, input, 2);
  }
  else if (THCudaTensor_nDimension(state, input) == 4)
  {
    batchSize = THCudaTensor_size(state, input, 0);
    classSize = THCudaTensor_size(state, input, 1);
    stride = THCudaTensor_size(state, input, 2)*
             THCudaTensor_size(state, input, 3);
  }
  else
  {
    THError("1D, 2D, 3D or 4D Tensor expected");
  }

  if (stride == 1)
  {
    dim3 grid(batchSize);
    dim3 block(1024);

  THCudaTensor_free(state, gradOutput);
  THCudaTensor_free(state, output);
}
