         // "The TU102 GPU also features 144 FP64 units (two per SM)... The FP64 TFLOP rate is 1/32nd the TFLOP rate of FP32 operation"
         case 7:
             switch (minor) {
-                // Volta
-                case 0:
+                // GV100
+                case 0:
+                    r.fp64 =  32;
+                    r.fp32 =  64;
+                    break;
+                // Xavier AGX (Volta)
+                // I cannot find docs but I can measure...
                 case 2:
-                    r.fp64 =  32;
-                    r.fp32 =  64;
-                    break;
-                // Turing
+                // TU102
                 case 5:
                     r.fp64 =   2;
                     r.fp32 =  64;

        // https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/NVIDIA-Kepler-GK110-GK210-Architecture-Whitepaper.pdf
        // "While the Maxwell architecture performs double precision calculations at rate of 1/32 that of single precision calculations..."
        case 5:
            r.fp64 =   4;
            r.fp32 = 128;
            break;
        // Pascal
        // GP100 = 6.0 https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf Table 1


        // memory bandwidth
        printf("memoryClockRate                         = %.3f GHz\n",  dp.memoryClockRate*1.e-6);
        printf("memoryBusWidth                          = %d bits\n",   dp.memoryBusWidth );
        printf("peak bandwidth                          = %.1f GB/s\n", dp.memoryClockRate*1.e-6 * dp.memoryBusWidth * 0.125);

        // memory capacity
        printf("totalGlobalMem                          = %zu bytes\n", dp.totalGlobalMem);
        printf("totalGlobalMem                          = %zu GiB\n",   dp.totalGlobalMem/(1<<30));

        // compute throughput
        printf("multiProcessorCount                     = %d\n",       dp.multiProcessorCount);
        printf("warpSize                                = %d\n",       dp.warpSize);
        printf("clockRate                               = %.3f GHz\n", dp.clockRate*1.e-6);

        cuda_flops_per_sm_s r = cuda_flops_per_sm(dp.major,dp.minor);
        printf("FP64 FMA/clock per SM                   = %d\n", r.fp64);
        printf("FP32 FMA/clock per SM                   = %d\n", r.fp32);
                                                                 // FMA=2 * ops/clock/SM * SMs * GHz
        printf("GigaFP64/second per GPU                 = %f\n", 2 * r.fp64 * dp.multiProcessorCount * 1.e-6*dp.clockRate);
        printf("GigaFP32/second per GPU                 = %f\n", 2 * r.fp32 * dp.multiProcessorCount * 1.e-6*dp.clockRate);


        // memory sharing characteristics
        printf("unifiedAddressing                       = %d\n", dp.unifiedAddressing);
