         // "The TU102 GPU also features 144 FP64 units (two per SM)... The FP64 TFLOP rate is 1/32nd the TFLOP rate of FP32 operation"
         case 7:
             switch (minor) {
-                // Volta
-                case 0:
+                // GV100
+                case 0:
+                    r.fp64 =  32;
+                    r.fp32 =  64;
+                    break;
+                // Xavier AGX (Volta)
+                // I cannot find docs but I can measure...
                 case 2:
-                    r.fp64 =  32;
-                    r.fp32 =  64;
-                    break;
-                // Turing
+                // TU102
                 case 5:
                     r.fp64 =   2;
                     r.fp32 =  64;

        // https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/NVIDIA-Kepler-GK110-GK210-Architecture-Whitepaper.pdf
        // "Each of the Kepler GK110/210 SMX units feature 192 single-precision CUDA cores,
        //  and each core has fully pipelined floating-point and integer arithmetic logic units."
        case 3:
            r.fp64 =  64;
            r.fp32 = 192;
            break;
        // Maxwell
        // https://developer.nvidia.com/blog/5-things-you-should-know-about-new-maxwell-gpu-architecture/

        // https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/NVIDIA-Kepler-GK110-GK210-Architecture-Whitepaper.pdf
        // "While the Maxwell architecture performs double precision calculations at rate of 1/32 that of single precision calculations..."
        case 5:
            switch (minor) {
                // Quadro M
                case 0:
                // Quadro etc
                case 1:
                // Jetson Nano
                case 2:
                    r.fp64 =   4;
                    r.fp32 = 128;
                    break;
            }
            break;
        // Pascal
        // GP100 = 6.0 https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf Table 1
