MODELING OF DIGITAL CMOS CIRCUITS USING TERNARY DECISIONS DIAGRAMS
The paper describes the logic simulation of digital CMOS circuits using ternary decisions diagrams(TDD). Also in this paper is done the interval estimation of power consumed by the scheme as an example of the use of such modeling. As an introduction there are explained representation of Boolean functions in the form of a binary decision diagram (BDD). To describe incompletely specified Boolean functions of the form f: Tn-> T, T = {0, U, 1} there are proposed the ternary decisions diagrams (TDD) and it’s special type - series-parallel ternary decisions diagrams (SP-TDD). On the basis of the SP-BDD representation of CMOS scheme explained the SP-TDD representation of CMOS scheme described the algorithm for constructing the SP-TDD model of CMOS circuits. Logical simulation of digital circuits using TDD enables optimization of digital circuits and estimation of the parameters of digital circuits with the gates in indeterminate state. In this paper is made logical modeling of digital CMOS circuit and estimation of the power consumed by the scheme. In the case of TDD the consumed power it is a interval value, as there are gates in the scheme with an undefined state, and therefore uncertain switching. Subsequently, these interval values can be improved by imposing additional information.