Distributed computing of fast Fourier transform in the FPGA architecture
Fast Fourier transform is executed based on single-type operations performed over two elements of the one-dimensional data array being processed. This paper presents the implementation of the single-type module, IP-core, which is used to perform fast Fourier transform on programmable logic integrated circuits of Virtex-6 family from FPGA class. The module includes the following blocks: a block of multiplying a complex number by a constant, four summators, two of which perform the addition operation, the other two - the subtraction operation in the reverse code, as well as registers that provide pipelining data and implemented on the basis of D - triggers included in the programmable logic integrated circuits of the Virtex-6 family. Thus, both configurable logic integrated circuits and memory elements (D-triggers) are used within FPGAs. This fact allows you to fully use the hardware resources of programmable logic integrated circuits FPGA class. The functional-logical modeling of the specified module is executed, estimates of hardware complexity and time of delay of functioning of the specified IP - core are received at use of specialized CAD-system ISE Design Suite 14,7. Due to the use of distributed data processing with the preservation of intermediate results for the IP - core, implemented on programmable logic integrated circuits of Virtex-6 family of FPGA class, the delay time of operation is approximately 10.4 ns., which corresponds to the processing frequency of the data array elements, equal to approximately 96.2 MHz. The results obtained open up the possibilities of studying the implementation of fast Fourier transform on distributed computing systems with programmable architecture the elements of which are FPGA-type arrays, both existing ones and promising ones.