The Problem of Element Placement on a Printed Circuit Board: the Solution Based on a Simplified Model of a Microstrip Line
One of the most important steps in complex digital systems design is the choice of optimal placement of elements on a printed circuit board (PCB). This becomes especially important when there is a lot of trancievers on parallel data bus. Particular attention is paid to providing integrity of signals and timing parameters. This article provides a simple technique for designing a conductor model that takes into account the parasitic parameters of the PCB, for a preliminary assessment of the quality of the component placement on the PCB. In most of modern CAD systems Wheeler or Hammerstad-Jensen microstrip models are used to calculate parasitic parameters of data lines. However, these models require complex computations which take a lot of time. Also, they require information about exact line location on the PCB. Often this information can be available only after component tracing. The proposed simplified microstrip model is based on Hammerstad-Jensen model and allows obtaining the values of resistance, capacitance, inductance and conductance per meter of a conductor line. The proposed methodic of calculating conductor line length allows to design transmission line model with parasitic parameters. The article discusses the RC, RLC, RLCG-line parasitic models. The proposed technique has been tested on the design, where DSP processor K1967VN028 was connected with FPGA and memory circuits with parallel data bus. Simulation in MicroCap 12 gives results that are much close to the ones that were obtained after traced PCB simulation with Cadence Sigrity and ADS.