Simulation of the Characteristics of a CMOS Logic Element of Matching Based on a STG DICE Cell for Content Addressable Memory at Charge Collection from Tracks of Single Nuclear Particles
The TCAD simulation of the 65-nm bulk CMOS matching logic element based on a STG DICE cell with the Exclusive OR combinational logic has been presented. This element is designed for the content addressable memory (associative memory) and the translation lookaside buffers for the 65-nm CMOS bulk technology. The combinational logic consists of two tristate inverters. The STG DICE (Spaced Transistor Groups DICE) is different from the standard DICE (Double Interlocked Cell) in that the transistors are separated into two groups. That is why charge collection from the track of single nuclear particles impacting on one of two groups does not lead to the upset state of this memory cell. Noise immunity of the matching element based on the STG DICE cell increases by the separation of its transistors into two blocks. Each block consists of one group of transistors of the STG DICE cell and transistors of one of two tristate inverters. Charge collection with tracks of nuclear particles has been simulated using tracks along the normal to the chip surface. Linear energy transfers on tracks were in the range of 10–60 MeV cm2/mg. Taking into account the silicon doping under the 400-nm-thick separating oxide layer, the main part of charges was collected from the layer of the silicon at depths of 400–850 nm from the surface of the chip. Data upsets in STG DICE cells with tracks along the normal to the chip surface were absent at charge collection from tracks onto the linear energy transfer up to 60 MeV cm2/mg. In the combinational Exclusive NOR logic, noise pulses up to 0.6 ns in the range of the energy transfer of 30–60 MeV cm2/mg can occur.  Keywords: logic element, simulation, single nuclear particle, failure tolerance, tracks of nuclear particles, memory cell