Green-oriented natural pipelining of digital circuits in FPGA-projects
The problem of reducing the power consumption for digital systems based on the FPGA chip element base is considered. The traditional ways of reducing energy consumption in digital systems are emphasized. A study of the possibilities for reducing energy consumption of digital systems is provided through the use of low-level features of the FPGA chip architecture. The paper shows that FPGA microchip architecture allows due to its internal cells resources to provide the diverse amount of serially connected computing units, created between pipelined stages in order to achieve the optimal correlation for the specific project and its productivity, hardware costs and power consumption. The expediency of using natural criteria for pipelining schemes in FPGA projects is demonstrated to improve performance and to reduce power consumption of any dynamic component.