AN AREA-EFFICIENT FPGA-BASED ARCHITECTURE FOR FULLY-PARALLEL STOCHASTIC LDPC DECODING
Stochastic decoding is a new alternative method of low complexity decoding of error correcting codes. This paper presents a variant of the hardware architecture for stochastic decoding low band codes. This architecture allows for full parallel decoding using the latest technologies when working with algorithms with LDPC, working on a field-programmable gate array (FPGA). The architecture of the parallel stochastic decoder is implemented on LDPC in device Xilinx Virtex - 4 XC4VLX200 with a bandwidth of 706 Mbit / s, at a bit error rate of about 10-6, with a loss of performance of about 0.1 dB. A survey of stochastic computing and stochastic decoding methods is also presented. The problem of hardware implementation and architecture of stochastic decoders are described. The results of the synthesis and decoding for the (1024,512) LDPC-codes with low density parity check decoder are presented. It is shown that the architectural features present in many programmable logic integrated circuits, can be used for area-efficient implementation of stochastic LDPC decoders