Concurrent design and verification of digital hardware
The main goal of this paper is to present a new design verification methodology for complicated digital systems, designed by high-level synthesis. This methodology is based on Algorithmic State Machine (ASM) transformations (composition, minimization, extraction, etc.), special algorithms for Data Path and Control Unit (CU) design, and very fast optimizing synthesis of finite state machines (FSM) and combinational circuits with hardly any constraints on their size, that is, the number of inputs, outputs, and states. Design tools supporting this methodology allow very fast implement, check and estimate many possible design versions, to find an optimized decision of the design problem and to simplify the verification problem for digital systems. In contrast to existent semi-formal approaches to verification of industrial systems, based on combination of simulation and formal verification approaches, a formalized method based on concurrency of synthesis and verification that is providing regular efficient way to verify the system designed properties starting from its semi-formal specification up to field programmable gate array (FPGA) implementation is considered.