The development of technology-independent metrics for evaluation of the masking properties of logic
Purpose. The main goal of this work is to develop a technology-independent metrics to estimate the fault-tolerance parameters of logic circuits. This formulation of the problem is due to the fact that often, in the early stages of the design, it is required to determine the vulnerability of the scheme to a single failure. Methodology. The article presents two technology-independent metrics to evaluate the masking properties of logic. Both metrics are based on the calculation of the observability of the circuit gates, providing a certain trade-off between accuracy and computational complexity, thus reducing the complexity from exponential to linear. The first metric is a generalized logic sensitivity coefficient. It does not depend on the probability of gate failure, so it can be used early in the design of fault-tolerant schemes. Another proposed method is for calculating the average fault-tolerance metric, the essence of which lies in the calculation of the upper and lower bounds for the error polynomial calculated based on the observability of the valves. Findings. It has been found that the proposed generalized logic fault sensitivity factor has several advantages, including low computational complexity and sufficient accuracy in most practical applications. On the set of benchmark circuits ISCAS’85, the studies were conducted to evaluate the accuracy of the proposed methods compared to traditional approaches. The obtained estimates indicate a high efficiency of the proposed methods. Originality/value. Although the methods of fault tolerance evaluation of logic circuits based on the observability are well known, the proposed metrics are new and have not been considered in previous publications.