Analysis of Project Source Files for Programmable Logic Integrated Circuits
Purpose: "System on a chip" CAD technology on the base of programmable logic integrated circuits includes extensive testing of the project. One of the methodological tools of testing is reverse engineering of microelectronic products when you study a completed product and find its software defects. To make the reverse engineering more efficient, the authors propose a technique for analyzing the structure of the project source files, helping to recognize software blocks or groups of circuit elements. Method: The structure of the project source files is analyzed, going from low-level description up to register transfer description. Results: By the example of an FPGA project, it was shown that a frame structure with a fixed size of words in files of BIT and RBT formats allows you to recover the logic of the system at the register transfer level, with the subsequent restoration of NCD and XDL files. It was suggested to present the project files in a format of named areas with the comments split into frames. This format is convinient for defining structural blocks and identifying internal connections. Practical relevance: The obtained results allow you to reduce the debugging time for "systems on chip" by identifying their configuration features which manifest themselves during the project compilation to CAD-generated files.