Circuit Design of Synchronizing Devices Within High-speed Data Services
The correctness of the information transmitted by information and communications systems and networks is largely determined by the quality of the synchronization system. The optimal circuit design for the construction of synchronizing devices and the entire system for maintaining synchronous operation, in this case, is of a crucial significance. In the research, we analyze and summarize the results of circuit simulation for several variants of the construction of synchronizing devices components, implemented within the framework of classical CMOS technology and circuit technology. The implementation of the proposed solutions on CMOS transistors with submicron design rules will require only the usage of new transistor models, which parameters are determined by a group of technological operations of their manufacturing process and inherent structural and technological limitations. This article describes methods of designing PLL components using SPICE models for CMOS transistors with design standards 1 - 2 pm (the model proposed by us) and 90 - 45 nm from Microwind. We propose classic circuit solutions to implement PLL components on bidirectional switches and inverters.