USING STOCHASTIC CALCULATIONS FOR IMPLEMENTATION NON-BINARY LDPC DECODER FPGA
This article presents a model of efficient hardware architecture for the decoder, built on non-binary block codes, low density parity check based on stochastic calculations. The developed architecture is focused on Xilinx Virtex devices and synthesis reports are summarized in the table. Once-worked architecture includes in its membership three main blocks: non-binary stream turns into a generator of stochastic numbers (converter of non-binary in stochastic representation), decoding al-algorithmically modules, namely a block control nodes and block check nodes, and the inverse transformation of the stochastic stream to the corresponding non-binary number. Designed as blocks integrated upper module. The top module is synthesized, it is focused on Xilinx Vertex and its metrics are summarized in the table, and produced power analysis. Conclusions about possible further optimization of the modified non-binary architecture using stochastic computing, and this optimization can also be used for higher-order Galois field with the analysis of the different parameters. Powered by modeling in a power dependency graphs used different logic elements in the architecture and the temperature dependence of the crystal of power