TEST GENERATION METHOD FOR DIGITAL DEVICES WITH STATE SUBSTANTIATION BASING ON GENETIC ALGORITHM
The aim of this paper is developing a test generation method for sequential digital devices at the logical level of description. Its main feature is the use of two phases for the construction of test of one selected fault. The first phase of method performs structural fault propagation in one clock cycle of model time, which well developed for this time. At end of this phase are formed the restrictions to the initial state of the fault and fault-free devices. Substantiation of this state is performed by using the new developed genetic algorithm. The use of such combined approach of test generation increases the effectiveness of this procedure for modern complex VLSI, which contains both data processing parts and controllers.