Comparative Analysis of the Error Pulses Formation at Outputs of Ttriple Majority CMOS Gates During Charge Collecting from Tracks of Single Ionizing Particles
The paper analyzes and compares triple majority gates designed on 65-nm bulk CMOS technology. The first majority gate is realized on NAND gates with a topological structure in which all the transistors of the output 3NAND gate are one by one introduced into groups of the same conductivity type transistors of three input 2NAND gates. The second majority gate is based on 2AND and 2OR logic gates. Third majority gate is realized on 2AND and 3OR gates. A special feature of the study is the classification and analysis of error pulses that occur at the outputs of majority gates when collecting charge from the tracks of single ionizing particles both before and after switching inputs of the gate. The study was carried out using 3D TCAD simulation with tracks at normal direction to the surface and linear energy transfer of 60 MeV*cm<sup>2</sup>/mg. Four types of error pulses formed at the outputs of all majority gates were observed. These are two types of error pulses formed before switching the inputs of the gate. The first is a pulse with the duration of the non-stationary state, which is formed if the time interval between the moment of the track occurrence and the moment of the beginning of switching signals at the inputs of the majority gate is longer than the duration of the non-stationary state. The second is the error pulse of the advanced switching of the gate, initiated by the charge collection from the track that occurs before switching signals at the inputs of the elements. In addition, there are two types of error pulses formed after switching the gate by inputs, namely, an error pulse with additional delay in switching the gate and an error pulse with duration of a non-stationary state formed after switching the inputs of the gate is completed. For tracks that occur after the completed switching of the gate by the inputs, an error pulse is formed with the duration of the non-stationary state that is characteristic of this input track point and the signal levels at the inputs. It has been found that the duration of the non-stationary state of AND and OR gates as parts of the majority gate during charge collection and simultaneous switching by inputs depends on the specific input track point into the group of transistors and the combination of input signal levels and practically does not depend on the moment of the track formation. The error pulses when changing the moment of track formation are shifted in time by a time interval equal to the offset of track formation moment relative to the moment of switching the inputs of the gate. The switching time of the majority gate on 2AND and 3OR varies from 9 ps to 600 ps, depending on the input track point and the input signals. The durations of non-stationary states, which determine the maximum values of the pulse durations of error signals formed at the outputs of the majority gates with advanced switching and the pulses that occur after the gate is completely switched by its inputs, have values of 420 ps for gate on NAND logic and for gate on 2AND and 2OR logic, and are 600 ps for the gate on 2AND and 3AND logic. The maximum values of error pulse durations with additional switching delay of the majority gate corresponding to the listed elements are 270 ps, 345 ps and 560 ps.