Layout Design Recommendations for Radiation-Hardened High-Density SRAM Cells
This article outlines the result of the efforts to design a radiation-hardened high-density SRAM for System-on-Chip integration. The SRAM is supposed to be exploited in space equipment. This circumstance prompted the designers to develop several architectural and circuit hardening measures. To evaluate the effectiveness of these measures, we used a SPICE based layout-aware simulation technique. In this work, we present the development process. The result of this process is a set of recommendations for layout design. The purpose of these recommendations is to reduce the multiplicity of the upset caused by a single charged particle. We used a spatial separation of two inverters with different well and body tie contacts as a parameter to conceive the recommendations. A memory cell, the layout of which follows the formulated recommendations, was used to build SRAM modules. The results of the simulations and irradiation experiments of the modules are presented in this article. The results have shown that following these recommendations can reduce the upset multiplicity rates to x3 - x4 at high LET and to x1 - x2 at low. The selected architectural solutions require the absence of failures with a multiplicity of more than x2 per line, which was possible to provide.