Correction of the Duration of Error Pulses in CMOS Combinational Logic Elements when Collecting Charge from Tracks of Single Particles
—The 3D-TCAD simulation of a noise pulse generation in CMOS combinational elements as a part of a majority element when collecting charge from tracks of single ionizing particles has been reported. The duration of noise pulses and its reducing in the logical elements by the 65-nm CMOS bulk technology with shallow trench isolation of transistor groups have been estimated. The simulation of the charge collection has been performed for a linear energy transfer of 60 MeV cm<sup>2</sup>/mg to a track. When the charge is collected from the particle track by the closed transistors of the NAND (NOR) elements, they transit to an open state (in particular, to the inverse offset mode). As a result, a noise pulse appears at the NAND (NOR) node, which closes the transistor of the output inverter of the AND (OR) element. The closed transistor of the inverter, collecting a charge from the same track, can compensate a part of the pulse duration when transmitting the pulse to the output of the AND (OR) element. Duplicating the inverter with the location of the main and additional transistors of the inverter on the boundary sides of the topological groups of NAND (NOR) transistors promotes reducing the duration of noise pulses when collecting a charge from the track of a single particle. Taking into account the correction, the duration of interferences occurring in the majority element is in the range of 50–300 ps.