FUSED MULTIPLY-ADD: METHODOLOGICAL ASPECTS
The paper presents approaches to designing self-timed (ST) equipment and analyzes conditions of in-system integration of synchronous and ST units in a supercomputer network taking the ST Fused Multiply-Add (FMA) unit as an example. Self-timed FMA complies with the IEEE 754 Standard and performs either one double precision FMA operation or one or two single precision operations simultaneously under three operands. It utilizes the ST-ternary encoding and the 65-nanometer CMOS (complementary metal-oxide-semiconductor) technology as the implementation basis. Depending on realization, it works with asynchronous or synchronous environment and provides not less than 1 GFlops performance with latency not more than 6 ns with respect to input data arrival.