Simulation of Transient Characteristics of Sub-100-nm Two-Phase CMOS Inverters
The simulation of the transient characteristics of the two-phase CMOS inverters according to the design standard 65 nm under the effect of the noise from an individual nuclear particle with an account of the capacitive couplings of the bus pairs, connecting the inputs and outputs of the inverters differential parts, has been performed. The values of these capacitances must be 2.5 - 3 times lower than those of the corresponding input (output) units. The relations of estimating the pulse contribution into the process of switching the two phase inverter have been obtained.