On approach to optimize manufacturing of field-effect heterotransistors framework circuit of a comparator with shared charge logic to increase their integration rate. On influence mismatch-induced stress
In this paper we introduce an approach to increase density of field-effect transistors framework a circuit of a comparator with shared charge logic. Framework the approach we consider manufacturing the comparator in heterostructure with specific configuration: the heterostructure should consist of a substrate with one or several epitaxial layers, which should include into itself several sections, manufactured by using another materials. These sections in epitaxial layers should be doped by diffusion or ion implantation. After that dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease value of mismatch-induced stress in the considered heterostructure. The approach based on modification of materials of heterostructure by radiation processing during ion implantation. Framework the approach materials of heterostructure near interface between layers of the structure could obtain lower density. We also introduce an analytical approach to analyze mass and heat transport in heterostructures during manufacturing of integrated circuits with account mismatch-induced stress. The approach gives a possibility to take into account spatial and temporal dependences of parameters of processes (diffusion and heat diffusion coefficients, charge carriers mobility, ...) at one time. At the same time the approach gives a possibility to take into account nonlinearity of considered processes.