Recurrent data-flow architecture: technical aspects of implementation and modeling results
New recurrent data-flow computational model and its possible implementation are introduced. The architectural prototype based on this model is positioned as DSP-type hardware. Research on possible implementations of the concept of multi-core dataflow recurrent architecture has lead to development of a recurrent signal processor incorporating the idea of two-level hybrid interaction between high-level (von Neumann) control unit and a low-level dataflow multi-core operational unit. Solutions to the key technical problems of dataflow DSP computing are demonstrated using the classical algorithm of fast Fourier transform (FFT) as an example. Super-scalar modes, recursion, manipulating constants, cycled operations and repetitive input data usage have been implemented. In order to show the perspectives of new architecture, the results of comparative analysis of number of logical steps needed to complete certain DSP algorithms are presented. Acceleration factors for the comparison of 4-core hybrid architecture recurrent signal processor to classic single-core microprocessor (dsPIC30F) range from 3 to 6 for word recognition algorithms and is estimated to be as high as 17 for FFT algorithm.