IMPLEMENTATION A LDPC DECODER OF LOW COMPLEXITY USING AN ALGORITHM MIN-SUM
This article is a resource-efficient decoder architecture based on low density codes. The algorithm used for the LDPC decoding algorithm is the min-sum. Decoder reduces complexity by limiting the internal connection posts on the outer circumference of 2 bits, and simplifies node checks. The simulation algorithm and the results show that the performance is better than the other algorithms. This algorithm can be introduced in a partially parallel architecture hardware to obtain significant savings in the hardware resources when implemented in a FPGA. The algorithms were simulated using MATLAB and compares BER performance of different algorithms. The modified algorithm min-sum (MMS) provides better performance, and can provide a significant reduction in the hardware resources in implementation. various types of hardware architectures have been studied. The total decoding time can be reduced by a more rapid convergence of the decoding algorithm and simple calculations. The fully parallel architecture requires a large amount of hardware resources, compared with a partially parallel architecture hardware. MMS algorithm when implemented in a partially parallel architecture hardware requires much less hardware for implementation