An all digital adaptive phase locked-loop based on the FPGA Xilinx Spartan-3A DSP
The concepts of an all digital phase locked-loop (ADPLL), which contains purely digital phase detector, loop filter, and nummericaly controlled osscilator, are explained. 2-nd and 3-rd order of astatism ADPLLs are considered and analysed using quasi-continious method. Implementation of the ADPLL, based on the FPGA Xilinx Spartan-3A DSP, and the experimental results in cases of working in AWGN and multipath channels, for input signal with constant frequency and with linear-frequency modulation, are presented. Potential application are also discussed