# 4. Logic Gates 4.1. Logic Gates.

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139
4. Logic Gates
4.1. Logic Gates.
Definition 4.1.1. Boolean algebra can be used to model circuit design in an
electronic device. Basic elements are gates. The three most common gates are
(1) Inverter:
x
x
(2) AND:
x1
x1x2 x ...xn
3
x2
.
.
.
xn
(3) OR:
x1
x1+ x2+ x3+ ...+ xn
x2
.
.
.
xn
Discussion
Gates are the basic building blocks of circuits. We combine gates to construct
combinatorial circuits or gating networks that have as output a given Boolean expression.
4.2. Example 4.2.1.
Example 4.2.1. Construct a combinatorial circuit for the function F given by the
following table:
4. LOGIC GATES
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
140
z F (x, y, z)
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
Solution.
x
y
z
x
y
+ + +
z
x
y
z
x
y
z
Discussion
The figure given in the solution to example 4.2.1 comes from the disjunctive normal
form for the function. The function is equivalent to xyz + xy z + xyz + x y z. This
4. LOGIC GATES
141
function is also equivalent to xy + x z, so the combinatorial network below also has
the same output.
y
x
+ xz
z
Clearly the network given here is simpler than the one given in the solution for
example 4.2.1. In this section we will not be concerned with simplifying the networks, only with getting the correct output using the gates discussed. Simplification
processes will be addressed in the next set of lecture notes.
4.3. NOR and NAND gates.
Definition 4.3.1. The NOR and NAND gates are given by
NAND
x
x|y
y
NOR
x
x y
y
Discussion
4. LOGIC GATES
142
Recall the definition of NAND and NOR from Representing Boolean Functions. It
was proven in that lecture that the sets {|} and {↓} are both functionally complete.
So a combinatorial circuit can always be created so that it consists only of NAND
gates or only of NOR gates.
4.4. Example 4.4.1.
Example 4.4.1. Construct a circuit for the output of the expression
x + yz
using only NAND gates.
Solution.
x
x|(y|z)
y
z
Discussion
We use the following to get the expression in terms of NAND operators only.
x + yz = (x)(yz) by DeMorgan’s Laws
= (x)|(yz) by the definition of NAND
= x|(y|z) by the definition of NAND.
We then use this expression to make the circuit.
The expression used for the solution of Example 4.4.1 is not the only possible
expression. We could have also found an expression for x + yz using the equivalences
x = x|x, xy = (x|y)|(x|y), and x + y = (x|x)|(y|y). Using these equivalences we
get x + yz = (x|x) + (y|z)|(y|z) = {(x|x)|(x|x)}|{[(y|z)|(y|z)]|[(y|z)|(y|z)]}. This
expression is much more complex than the one used for the solution in Example
4.4.1, though!
Exercise 4.4.1. Construct a circuit for the output of the expression in Example
4.4.1 using only NOR gates.
4. LOGIC GATES
143
Definition 4.5.1. The half adder circuit has as input the variables x and y and
has as output the variables s and c given by the table.
Input
x y
0 0
0 1
1 0
1 1
Output
s c
0 0
1 0
1 0
0 1
The functions c = xy and s = (x + y)(xy) give the correct output for these
functions. Therefore, the circuit for the half adder follows:
x
s=(x+y)(xy)
c=xy
Definition 4.6.1. The full adder circuit has as input the variables x, y, and ci
and has as output the variables s and ci+1 given by the table.
4. LOGIC GATES
Input
x y ci
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
144
Output
s ci+1
0 0
1 0
1 0
0 1
1 0
0 1
0 1
1 1
We can use the half adder to calculate the full adder as shown in the circuit below.
ci
(x+y)(xy)
x
y
Half
Half
xy
c i+1
Discussion
Recall from Applications of Number Theory the algorithm for adding two integers
a and b written in base 2:
Let a = (an−1 an−2 &middot; &middot; &middot; a1 a0 )2 and b = (bn−1 bn−2 &middot; &middot; &middot; b1 b0 )2 , and suppose the sum of
a and b is s = (sn sn−1 sn−2 &middot; &middot; &middot; s1 s0 )2 . Note that if the binary expansions for a and b
do not have the same number of digits we add zeros to the left of the smaller one to
make them the same length.
Since s = a + b we have
a0 + b0 = 2c0 + s0
a1 + b1 + c0 = 2c1 + s1
a2 + b2 + c1 = 2c2 + s2
4. LOGIC GATES
145
..
.
an−1 + bn−1 + cn−2 = 2cn−1 + sn−1
sn−1 = cn−1 .
At the first stage of the addition we only add the first bits of a and b and get out
the values for c0 and s0 . The half adder gives us this operation. In fact, the half adder
gives us a “first stage” of each of the following additions as well. However, we must
go further than adding the bits of a and b to get the carries and sums on subsequent
stages because we must also consider the carry from the previous addition. The full
adder gives us the carry and sum when we input the appropriate bits for a and b and
the previous carry.
Exercise 4.6.1. Explain each stage of the algorithm used to find the sum of the
binary numbers 1011 and 110 by giving each step including which adder is used and
its input and output.
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